PCAL6524HE - Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset

PCAL6524HE是NXP恩智浦公司的一款I²C增强快速模式产品，PCAL6524HE是Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset，本站介绍了PCAL6524HE的封装应用图解、特点和优点、功能等，并给出了与PCAL6524HE相关的NXP元器件型号供参考。

PCAL6524HE - Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander with Agile I/O features, interrupt output and reset - I²C增强快速模式 - I²C - 恩智浦

产品描述

The PCAL6524 is a 24-bit general purpose I/O expander that provides remote I/O expansion formost microcontroller families via the Fast-mode Plus (Fm+) I2C-bus interface.The ultra low-voltage interface allows for direct connection to a microcontrolleroperating down to 0.8 V.

NXP I/O expanders provide a simple solution when additional I/Os are needed while keepinginterconnections to a minimum, for example, in battery-powered mobile applications forinterfacing to sensors, push buttons, keypad, etc. In addition to providing a flexibleset of GPIOs, it simplifies interconnection of a processor running at one voltage leveldown to 0.8 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V. ThePCAL6524 has built-in level shifting feature that makes these devices extremely flexiblein mixed power supply systems where communication between incompatible I/O voltages isrequired, allowing seamless communications with next-generation low voltagemicroprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals ata higher voltage on the port side.

There are two supply voltages for PCAL6524: VDD(I2C-bus) andVDD(P). VDD(I2C-bus) provides the supply voltage for the interfaceat the master side (for example, a microcontroller) and the VDD(P) providesthe supply for core circuits and Port P. The bidirectional voltage level translation inthe PCAL6524 is provided through VDD(I2C-bus). VDD(I2C-bus) shouldbe connected to the VDD of the external SCL/SDA lines. This indicates the VDDlevel of the I2C-bus to the PCAL6524, while the voltage level on Port P ofthe PCAL6524 is determined by the VDD(P).

The PCAL6524 fully meets the Fm+ I2C-bus specification at speeds to 1 MHz andimplements Agile I/O, which are additional features specifically designed to enhance theI/O. These additional features are: programmable output drive strength, latchableinputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt statusregister, programmable open-drain or push-pull outputs.

Additional Agile I/O Plus features include I2C software reset and device ID.Interrupts can be specified by level or edge, and can be cleared individually withoutdisturbing the other interrupt events. Also, switch debounce hardware isimplemented.

At power-on, the I/Os are configured as inputs. However, the system master can enable theI/Os as either inputs or outputs by writing to the I/O configuration bits. The data foreach input or output is kept in the corresponding input or output register. The polarityof the Input Port register can be inverted with the Polarity Inversion register, savingexternal logic gates. Programmable pull-up and pull-down resistors eliminate the needfor discrete components.

The power-on reset puts the registers in their default state and initializes theI2C-bus/SMBus state machine. The RESET pincauses the same reset/initialization to occur without depowering the part. The systemmaster can also accomplish a reset via an I2C command and initialize allregisters to their default state.

The PCAL6524 open-drain interrupt (INT) output is activatedwhen any input state differs from its corresponding Input Port register state. As well,the INT output can be specified to activate on input pinedges. There are a large number of interrupt mask functions available to maximizeflexibility.

INT can be connected to the interrupt input of a microcontroller.By sending an interrupt signal on this line, the remote I/O can inform themicrocontroller if there is incoming data on its ports without communication via theI2C-bus. Thus, the PCAL6524 can remain a simple slave device. The inputlatch feature holds or latches the input pin state and keeps the logic values thatcreated the interrupt until the master can service the interrupt. This minimizes thehost’s interrupt service response for fast moving inputs.

The device Port P outputs have 25 mA sink capabilities for directly driving LEDs whileconsuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I2C-busaddress and allow up to four devices to share the same I2C-bus or SMBus.

产品特性和优势

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