The PCA9641 is a 2-to-1 I2C master demultiplexer with an arbiter function. It is designedfor high reliability dual master I2C-bus applications where correct system operation isrequired, even when two I2C-bus masters issue their commands at the same time. Thearbiter will select a winner and let it work uninterrupted, and the losing master will takecontrol of the I2C-bus after the winner has finished. The arbiter also allows for queuedrequests where a master requests the downstream bus while the other master hascontrol.

A race condition occurs when two masters try to access the downstream I2C-bus atalmost the same time. The PCA9641 intelligently selects one winning master and thelosing master gains control of the bus after the winning master gives up the bus or thereserve time has expired.

Multiple transactions can be done without interruption. The time needed for multipletransactions on the downstream bus can be reserved by programming the Reserve Timeregister. During the reserve time, the downstream bus cannot be lost.

Software reset allows a master to send a reset through the I2C-bus to put the PCA9641’sregisters into the power-on reset condition.

The Device ID of the PCA9641 can be read by the master and includes manufacturer,device type and revision.

When there is no activity on the downstream I2C-bus over 100 ms, optionally thePCA9641 will disconnect the downstream bus to both masters to avoid a lock-up on theI2C-bus.

The interrupt outputs are used to provide an indication of which master has control of thebus, and which master has lost the downstream bus. One interrupt input (INT_IN) collectsdownstream information and propagates it to the two upstream I2C-buses (INT0 andINT1) if enabled. INT0 and INT1 are also used to let the master know if the shared mailbox has any new mail or if the outgoing mail has not been read by the other master. Thoseinterrupts can be disabled and will not generate an interrupt if the masking option is set.

The pass gates of the switches are constructed such that the VDD pin can be used to limitthe maximum high voltage, which will be passed by the PCA9641. This allows the use ofdifferent bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicatewith 3.3 V devices without any additional protection.

The PCA9641 does not isolate the capacitive loading on either side of the device, so thedesigner must take into account all trace and device capacitances on both sides of thedevice, and pull-up resistors must be used on all channels.

External pull-up resistors pull the bus to the desired voltage level for each channel. All I/Opins are 3.6 V tolerant.

An active LOW reset input allows the PCA9641A to be initialized. Pulling the RESET pinLOW resets the I2C-bus state machine and configures the device to its default state asdoes the internal Power-On Reset (POR) function.

• 2-to-1 bidirectional master selector
• Channel selection via I2C-bus
• I2C-bus interface logic; compatible with SMBus standards
• 2 active LOW interrupt outputs to master controllers
• Active LOW reset input
• Software reset
• Four address pins allowing up to 112 different addresses
• Arbitration active when two masters try to take the downstream I2C-bus at the sametime
• The winning master controls the downstream bus until it is done, as long as it is withinthe reserve time
• Bus time-out after 100 ms on an inactive downstream I2C-bus (optional)
• Readable device ID (manufacturer, device type, and revision)
• Bus initialization/recovery function
• Low Ron switches
• Allows voltage level translation between 1.8 V, 2.3 V, 2.5 V, 3.3 V and 3.6 V buses
• No glitch on power-up
• Supports hot insertion
• Software identical for both masters
• Operating power supply voltage range of 2.3 V to 3.6 V
• All I/O pins are 3.6 V tolerant
• Up to 1 MHz clock frequency
• ESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM perJESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: TSSOP16, HVQFN16

• High reliability systems with dual masters
• Gatekeeper multiplexer on long single bus
• Bus initialization/recovery for slave devices without hardware reset
• Allows masters without arbitration logic to share resources

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