The 74LVC30A is an 8-input NAND gate.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of thesedevices in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and falltime.

This device is fully specified for partial power-down applications using IOFF.The IOFF circuitry disables the output, preventing the damaging backflow current throughthe device when it is powered down.

• Wide supply voltage range from 1.2 V to 3.6 V
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Complies with JEDEC standard:
  • JESD8-7A (1.65 V to 1.95 V)
  • JESD8-5A (2.3 V to 2.7 V)
  • JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
  • HBM JEDEC JS-001-2012 exceeds 2000 V
  • MM JESD22-A115-C exceeds 200 V
  • CDM JESD22-C101F exceeds 1000 V
• Specified from ?40 °C to +85 °C and ?40 °C to +125 °C

• BGU6104 - 宽带硅低噪声放大器MMIC
• BUK7675-55A - N沟道TrenchMOS标准电平FET
• TJA1028 - 集成电压调节器的LIN收发器
• UJA1132HW - Buck/boost HS-CAN/dual LIN system basis chip
• 74AHCT377PW - 带数据使能的八频D型触发器；正沿触发器
• NX3L1G384GW - 低电阻单刀单掷模拟开关
• BZB984-C5V1 - 双倍稳压器二极管
• MFRC52202HN1 - 标准3V MIFARE读卡器解决方案，版本2.0
• BC869 - 20 V，2 A PNP中等功率晶体管
• HEF4066B - 四路单刀单掷模拟开关